Whenever certain circuits of an integrated device require supply, control or biasing voltages higher than the power supply voltage of the integrated device, it is a general practice of integrating dedicated charge-pump voltage multipliers for generating a boosted voltage of the required level.
Often the boosted voltage generated by a common charge-pump circuit needs to be regulated for ensuring a correct bias. That is, a boosted voltage that remains within a specified range notwithstanding the current absorbed by the biased load or circuit. In these cases a dedicated circuit for regulating the voltage on an output node of the regulator to which the circuit or load to be powered, biased or controlled is connected. This configuration may generally be equated to a capacitive load. Similarly, a capacitance that eventually may be charged at a high voltage, e.g., at a charge-pump boosted voltage, may need to be discharged in a controlled manner such as with a certain discharge circuit. Also in this case, a dedicated regulating circuit needs to be integrated.
An important example of an integrated device with these requirements is a non-volatile memory device that commonly requires biasing voltage levels higher than the power supply voltage of the device during program/erase phases of operation. For example, in a multi-level flash memory device of a NAND type, program/erase operations may require boosted voltages starting from around 10V and up to about 20-22V.
In one-bit/cell flash memories, such a dedicated voltage regulator may be omitted and the output voltage of the charge-pump circuit can be employed directly, without any regulation, by relying solely on the ON-OFF control of the charge-pump circuit that generates the boosted voltage. In one-bit/cell flash memories, a ripple of about 1V to 3V on the boosted voltage output by the ON-OFF controlled charge-pump circuit is generally tolerable.
In contrast, in multi-level memory devices, where more bits can be stored in each single cell of the memory array, the much higher precision that is required for the biasing voltages makes indispensable integration of a dedicated boosted voltage regulator to reduce the amplitude of the ripple on the output biasing voltages that are required during different phases of operation of the memory.
Similar requirements of precision for the output boosted voltages are encountered also in other integrated devices, in which cases the same requirement of integrating a dedicated regulating circuit of the boosted voltages generated by the charge-pump circuit arises.
On a different account, fabrication technologies of integrated devices strive to contain costs. This cost awareness of chip manufacturing, especially for devices designed for mass production and intended primarily for consumer markets, imposes to produce devices at the lowest price per unit as possible. Technological advances in silicon processing are exploited to reduce the number of critical processing steps and the number of masks required.
As noted above, an important example of this category of integrated devices are non-volatile memories. The fabrication technology of non-volatile memories is so streamlined for reducing costs that it does not generally permit formation along the normal low voltage (LV) CMOS structures special high voltage (HV) structures unless additional processing steps and relative masks are introduced for realizing the high side transistor of the CMOS structure. High voltage structures include transistors capable of withstanding a relatively high voltage. For a NAND type flash memory, which is generally supplied with positive voltages, both for the normal power supply voltage and for charge-pump boosted voltages, the high voltage transistor is the PMOS transistor. The low side transistor, generally the NMOS transistor, may be realized with an appropriate high voltage structure where needed without significant changes in terms of costs of the fabrication process.
According to the most common fabrication processes of these types of integrated devices, the PMOS transistor of the CMOS pair (PMOS+NMOS) is the critical structure that does not admit voltage differences among its terminals (source, drain, gate and bulk) above about 4V to 5V, as readily known by those skilled in the art.
When a positive boosted voltage regulating circuit to be supplied at an unregulated charge-pump boosted voltage in the range of 20-24V is required for fabricating a multilevel non-volatile flash memory, the normal low voltage PMOS transistor structure of the voltage regulator that is realized with the processing steps of any low cost one bit/cell flash memory fabrication process may often be intrinsically unsuitable. Therefore, additional costs of modifying the normal process introducing additional dedicated masks for realizing a high voltage PMOS structure cannot be avoided.
To illustrate the problem, FIG. 1 shows a typical multistage circuit powered at an unregulated charge-pump boosted voltage VPUMP for regulating the voltage VOUT. In the example shown, the first stage is a differential stage, to a first input of which is coupled a reference (control) voltage VREF and to a second input of which a scaled replica VFEED of the output voltage VOUT is fed back. The output stage is a PMOS transistor MPOUT that necessarily needs to have a high voltage structure in order to withstand the relatively high level of VPUMP, which is the unregulated charge-pump output voltage.
In fact, as already mentioned, a similar problem of handling a charge-pump boosted voltage without integrating transistor structures of a conductivity type for the sign of the boosted voltage with special high voltage characteristics, arises when a capacitance that is eventually charged at a boosted voltage needs to be discharged with a current regulated by a dedicated regulating circuit.